Data may be communicated between different modules of a hardware system through a bus. The bus may be shared during communications between different modules. For example, the bus may be shared between an external host, a NAND, a NOR, a synchronous/asynchronous SRAM style interface (e.g., devices such as Wi-Fi). The shared pins may not provide a bandwidth required because of stalling (e.g., delays) during sharing of data across the bus. The shared pins may not be able to provide constant flow of data required for different application threads running on a processor requiring data from different external interfaces.
The bus may be formed with additional pins to minimize delays. The additional pins may increase costs of a device (e.g., a circuit) and may take up additional device area. As a result, a cost of the device may increase and the device may not operate when requirements require lower cost and smaller size (e.g., when a device is pin limited).